San Francisco– Intel on Tuesday took the veils off its Agilex family of Field Programmable Gate Arrays (FPGAs) that aim to provide customised solutions to address data-centric workloads across embedded, network and data centre markets.
Expected to start coming with devices in the third quarter of this year, the Agilex family is part of a new wave of more easily programmable FPGAs which is beginning to take an increasingly central place in computing as data centres are called on to handle an explosion of data.
“The race to solve data-centric problems requires agile and flexible solutions that can move, store and process data efficiently. Intel Agilex FPGAs deliver customised connectivity and acceleration while delivering much needed improvements in performance and power for diverse workloads,” Dan McNamara, Intel Senior Vice President, Programmable Solutions Group, told reporters here.
The Intel Agilex family combines FPGA fabric built on Intel’s 10 nanometer (nm) process with innovative heterogeneous 3D SiP technology. This provides the capability to integrate analog, memory, custom computing, and Intel eASIC device tiles into a single package with the FPGA fabric.
Intel Agilex FPGAs are also the first processors to support Compute Express Link (CXL) which is a high-speed interconnect designed to maintain memory coherency among CPUs such as the second-generation Xeon Scalable processors and FPGAs and GPUs.
It ensures that different processors do not clash when trying to write to the same memory space, thus, allowing CPUs and accelerators to share memory.
The Santa Clara, California-headquartered company delivers a custom logic continuum with reusable IPs through a migration path from FPGA to structured application-specific integrated circuit (ASIC).
Intel Agilex will support DDR5, high-bandwidth memory (HBM) and Intel Optane DC across three series.
The company’s second-generation HyperFlex architecture helps give Agilex 40 per cent higher performance than the company’s current high-end FPGA family — the Stratix 10 line. (IANS)
