New Delhi — IBM on Thursday unveiled what it called the world’s first chip technology built on a process node smaller than 1 nanometer, marking a major advance as the semiconductor industry approaches the physical limits of conventional chip scaling.
The U.S. technology company said the chip uses a 0.7-nanometer, or 7-angstrom, process and a new three-dimensional transistor architecture known as nanostack.
The technology is designed to improve chip performance and energy efficiency at atomic-scale dimensions. It can fit nearly 100 billion transistors onto a device roughly the size of a fingernail, nearly twice the transistor density of IBM’s 2-nanometer technology unveiled in 2021.
IBM said the new process could deliver up to 50 percent higher performance or 70 percent greater energy efficiency than chips built using its 2-nanometer node.
The technology could support computing-intensive applications including generative artificial intelligence, cloud infrastructure and next-generation electronic devices.
“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometre era to the scale of atoms,” said Jay Gambetta, Director of IBM Research and IBM Fellow.
IBM said the nanostack architecture vertically stacks and staggers transistors, allowing more components to fit on a chip. The design also enables different materials to be optimized independently for performance and power efficiency.
Company researchers also demonstrated improvements in static random-access memory scaling, which could help chip designers develop more efficient processors for high-bandwidth AI workloads.
IBM expects the technology’s earliest commercial applications to emerge within the next five years.
The research was conducted at IBM’s semiconductor research facility in Albany, New York, in collaboration with ASML, Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions. (Source: IANS)
